<-[[.:start]] ====== Photos ====== ** Some pics of the project ** ===== Version 1 - veroboard ===== {{:public:computers:6502:img_20220929_081619_102_1.jpg?400|}} Mark 1 in all its glory {{:public:computers:6502:img_20220929_081651_164_1.jpg?400|}} Twin LCD displays. 2-line for RTC and Uptime. 4 Line for monitor. {{:public:computers:6502:img_20220929_081729_937_1.jpg?400|}} RTC Chip and 2 debounced push buttons on the top breadboard. RTC is fed with 32.768kHz from a function generator awaiting for a new xtal. 4-input AND gate for VIA IRQ connection to CPU on the other breadboard. {{:public:computers:6502:img_20220929_081737_023_1.jpg?400|}} I/O board with 2 65C22 VIAs. Beeper piezo sounder in the Altoids tin. {{:public:computers:6502:img_20220929_081741_790_1.jpg?400|}} ===== Version 2 ===== * Planned to be built using Wirewrap methods but seems to have been forgotten about * I'll possibly return to the project in winter 2024/5? --- //John Pumford-Green 29/09/22 08:21// ===== Further Information ===== {{tag>}}